Field of the Invention
The invention relates to an integrable, controllable delay device having an input connection for an input signal which is to be delayed, an output connection for a delayed output signal, and a control connection for a control signal which controls the delay time. The invention also relates to use of such an integrable, controllable delay device. Finally, the invention relates to a method in order to delay a clock signal, using such a delay device.
Such integrable, controllable delay devices are widely used for delaying a clock signal in integrated semiconductor circuits. One particular application of the delay device is in a delay control loop. Delay control loops are used in digital circuits in order to produce clock signals at a specific phase angle. By way of example, synchronously operated integrated semiconductor memories, which operate on the double data rate principle, so-called DDR SDRAMs (double data rate synchronous random access memories) use a delay control loop in order, taking account of internal signal delay times, to produce a clock signal on the output side, which produces data that is to be emitted, in synchronism with an input clock signal which is supplied to the integrated circuit at some other point.
A delay control loop compares the clock signal which is supplied to the input side of the delay unit with the delayed clock signal which is produced on the output side, and readjusts the delay as a function of the phase difference until the phase difference is regulated as closely as possible to zero. It is particularly important for the clock on the output side to be as stable as possible and to be free of jitter. For example, the clock on the output side is intended to be influenced as little as possible by fluctuations in the supply voltage, and its current delay time setting is intended to be independent of the drive to the delay unit.
One known delay device is in the form of a so-called tapped delay line. In this case, inverters are connected in series. The signal that is delayed along the delay line can be tapped off via signal paths which branch off from the delay line. The signal paths are coupled to a common node on the output side. These branching signal paths each contain a tristate inverter, which either passes on the signal which is to be delayed, or is switched to produce a high impedance. The output-side node has a high capacitance, which is proportional to the number of inverter stages in the delay line. The tristate inverters switch relatively slowly. Once the signal has been tapped off from the chain of inverters, it is also necessary to take account of the signal delay produced by the tristate inverter and any inverter which there may be downstream. Finally, an inverter in the delay line has to drive two input loads which are connected to it on the output side, namely the downstream inverter in the delay line, and the input of the tapping tristate inverter.
European patent EP 0 570 158 B1 (DE 693 27 612 T2) and U.S. Pat. Nos. 5,336,939 and 5,359,232 disclose a circuit for producing a stable clock signal on the basis of frequency multiplication. The circuit contains a delay stage with a variable delay time, wherein two multiplexers are connected in series. A signal is supplied firstly without any delay and secondly via delay elements as well, to the input sides of the multiplexers.
U.S. Pat. No. 6,329,854 B1 and the corresponding German patent application DE 199 12 967 A1 disclose a delay control loop with a delay path wherein multiplexers are provided, whose input connections can be connected to one another via flipflops. All the multiplexers are driven at the same time, either by an UP control signal or by a DOWN control signal.
U.S. Pat. No. 5,465,076 and the corresponding German patent application DE 43 27 116 A1 disclose a programmable delay line, wherein multiplexers are used to whose inputs an input signal can be supplied directly and, in addition, with a delay.
It is accordingly an object of the invention to provide an integrable and controllable delay unit, its utilization in a control loop, and a signal delay method, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the delay device has a delay time that can be set as exactly as possible, so that a largely stable, jitter-free output clock can be produced when this delay device is used in a delay control loop. In particular, the output clock is intended to be as independent as possible of manufacturing-dependent fluctuations in the component parameters, supply voltage fluctuations or temperature fluctuations.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrable, i.e., integratable, controllable delay device, comprising:
an input terminal for receiving an input signal to be delayed;
an output terminal for outputting an output signal delayed with respect to the input signal;
a control connection for receiving a control signal controlling a delay time;
a multiplicity of multiplexers each having a first input, a second input, and an output connection;
the multiplexers forming a series circuit with downstream multiplexers and upstream multiplexers in a signal flow direction, with the second connection of a respective downstream multiplexer connected to the output of a respective upstream multiplexer, and the first connection of each the multiplexer connected to the input; and
the second connection of one of the multiplexers being connected to reference potential, and the output of another of the multiplexers being coupled to the output terminal.
In other words, the objects are achieved by an integrable, controllable delay device which comprises an input connection for an input signal which is to be delayed, an output connection for a delayed output signal, a control connection for a control signal which controls the delay time; a large number of multiplexers each having a first and a second input connection and one output connection, with the multiplexers being connected in series by connecting the second connection of a downstream multiplexer to the output of an upstream multiplexer and by coupling the first connections of all the multiplexers to the input connection, with the second connection of one of the multiplexers being connected to a connection for a reference potential, and the output of another of the multiplexers being coupled to the output connection.
With the above and other objects in view there is also provided, in accordance with the invention, the above-outlined delay device in combination with a delay control loop. The delay device is connected in the delay control loop such that a delay time of the delay device is readjusted in dependence on a phase difference between a clock signal input to the delay device and an output signal carried at the output of the delay device.
With the above and other objects in view there is also provided, in accordance with the invention, a method for delaying a clock signal. The method comprises the following steps:
providing an integrable, controllable delay device according to the above summary;
inputting the clock signal to be delayed at the input terminal and providing a control signal formed with a number of bits at the control connection of the delay device;
setting a switch position of two series-connected multiplexers in dependence on the bits of the control signal such that a connection is established in each case for passing on the clock signal to be delayed between the first signal input and the output connection of the two multiplexers;
setting a switch position of all other multiplexers such that a signal connection is produced between the second input connection and the output connection thereof;
outputting a delayed clock signal at the output terminal of the multiplexer connected last in the series circuit;
defining a phase difference between a first signal derived from the clock signal to be delayed and a second signal derived from the delayed clock signal; and
generating the control signal in dependence on the phase difference between the first and second signals.
In other words, the method comprises these steps: provision of the clock signal to be delayed at the input connection and provision of the control signal, which comprises a number of bits, at the control connection; setting of the switch position of two series-connected multiplexers as a function of the bits of the control signal such that a connection which passes on the clock signal which is to be delayed is in each case produced between its first signal input and its output connection; setting of the switch position of all the other multiplexers such that a signal connection is produced between their second input connection and their output connection; production of a delayed clock signal at an output connection of the multiplexer which is arranged last in the series circuit; and formation of a phase difference between a signal, from which the signal to be delayed is derived, and from a further signal, which is derived from the delayed clock signal; and production of the control signal as a function of the defined phase difference.
In the delay device according to the invention, multiplexers are provided in order to form the signal delay time that is applied to the signal which is to be delayed. One of the inputs and one output of all the multiplexers are connected in series with one another. The other input of the multiplexers is coupled jointly to a node, and is connected to that connection which produces the input signal which is to be delayed.
Depending on the required delay time, the input signal which is to be delayed is injected into the series circuit at one of the multiplexers. A different delay time is produced, depending on the number of effective multiplexer stages which the signal has to pass through before reaching the output. The output signal is tapped off at the output of the last multiplexer connected in the series circuit. One of the inputs of the first multiplexer in the series circuit is connected to a constant potential, preferably ground.
The configuration of the delay device with multiplexers has the advantage that the respective capacitive load, to be driven on the output side, of the multiplexers and of the output of the last multiplexer stage as well remains the same independently of the respective delay time setting. The variation which is formed as a function of the delay time setting occurs on the input side. Capacitive fluctuations resulting from this in the capacitive load on the input side can be compensated for by a suitably powerful driver which produces the input signal which is to be delayed. The delay unit according to the invention has the advantage that the signal which is to be delayed is not subject to any capacitive load fluctuation that is dependent on the delay time. This driver may be a conventional inverter, which switches more quickly than a tristate inverter in a tapped delay line. The output of a multiplexer is connected only to the input of a single further downstream multiplexer. Compared with a tapped delay line, the delay unit formed by a multiplexer switches more quickly than the corresponding unit in the tapped delay line.
The delay unit is preferably designed to process differential signals. This means that a complementary, inverted signal is processed at the same time as each signal. This compensates for the influence of supply voltage fluctuations of the delay time. Each of the multiplexers has a particularly advantageous circuitry configuration, which is suitable for processing differential signals. When this delay unit is used in a delay control loop, a relatively jitter-free output clock signal is produced, even in different operating conditions.
Each of the multiplexers expediently has four current paths, which are connected at one end to a current source and are coupled via this to a first pole of a supply voltage, for example ground. The other ends of the four current paths are coupled in pairs to respective resistance elements. The signal is injected differentially into the four current paths. In order to obtain even better independence from fluctuations in the supply voltage, a capacitance is connected in parallel with the current source in order to compensate for and damp out corresponding fluctuations resulting from switching operations on currents between the four current branches. The resistance elements are preferably in the form of transistors connected as diodes, preferably so-called MOS diodes. The diodes are connected to the second pole of the supply voltage. In consequence, the current branches are also largely decoupled from the second pole of the supply voltage. It is even more advantageous for an MOS transistor, which is connected as a current source, to be connected in parallel with the diode. The control connection of this transistor is driven by a constant potential. The parallel circuit formed from the MOS diode and MOS current source may be referred to as an active resistance or linearized transistor.
In detail, the current paths each contain two MOS transistors, whose controlled paths are connected in series. One of the switches in the first and second current paths is in each case controlled jointly by a line of the control signal which sets the delay time. The comparable transistors in the third and fourth current paths are switched jointly by the complementary signal component of the control signal. The other transistors in the first and second current paths are connected to the complementary signal outputs of a multiplexer which is connected upstream in the chain of delay elements. The other transistors in the third and fourth current paths are driven by the complementary signal parts of the input signal, that is to say by the common input connection. Those ends of the current paths which are connected to the active resistance are connected to one another crossed over. The first and third current paths are connected to one active resistance, and the second and fourth current paths are connected to the other active resistances.
Depending on the delay time to be set, one of the multiplexers is set such that its output is connected to its first of the two input connections. The clock signal which is to be delayed is injected into the chain of series-connected multiplexers at this point. All the other multiplexers, both those upstream and those downstream, are set such that their output produces a signal connection to their respective second input.
In one particularly advantageous refinement of the setting of the delay device, two of the multiplexers are set such that their output is connected to their respective first input in order to form a signal connection. These multiplexers are expediently connected directly in series, that is to say the output of the first of these two series-connected multiplexers is connected directlyxe2x80x94without the interposition of a further multiplexerxe2x80x94to the second input connection of the downstream one of these multiplexers. In this case, the clock signal which is to be delayed is injected, as before, into the multiplexer chain at the second of the directly series-connected multiplexers, in order to produce the delay. The clock signal which is to be delayed is at the same time also available on the output side of the first of the two directly series-connected multiplexers. However, it is not yet passed on by the second of the multiplexers. The second of the multiplexers is switched only if the delay time is to be increased by one step element, wherein case the clock signal which is to be delayed and is already present at its second input can be passed on directly to its output. The signal form of the output signal from the delay device is improved. In particular, no disturbance pulses, so-called glitches, are produced.
The multiplexers which are connected upstream in the multiplexer chain of the multiplexers considered above, which are connected directly in series, are expediently switched off in order to save power. This is particularly advantageous in the embodiment, specified above, of the multiplexers as current switches comprising at least four current paths and a current source.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrable, controllable delay device, use of a delay device, and a method for delaying a clock signal using a delay device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.